1. Field of the Invention
The invention relates to a semiconductor chip package, more particularly to a lead frame for a semiconductor chip package, a semiconductor chip package that incorporates multiple integrated circuit chips, and a method of fabricating a semiconductor chip package with multiple integrated circuit chips.
2. Description of the Related Art
In the packaging of a semiconductor chip, a lead frame is needed to load the chip and to provide terminal pins for bonding with pads on the chip to permit access to the chip externally of the semiconductor chip package. The bonded chip is encapsulated to fasten the same on the lead frame, to isolate the chip from the outside for protection, and to facilitate use of the chip in the circuit board of an electronic system.
FIG. 1 illustrates a conventional semiconductor chip package 1 that includes a lead frame 10. The lead frame 10 has a frame body that serves as the loader for a single integrated circuit chip 11, and that is formed with a chip-receiving window 12 for placing the integrated circuit chip 11 therein. The frame body of the lead frame 10 is further provided with connection leads 13 that extend outwardly from the frame body to serve as terminal pins for conducting the signals of the integrated circuit chip 11 to the exterior of the semiconductor chip package 1. Bonding pads 110 on the integrated circuit chip 11 are usually wire-bonded to the connection leads 13 for electrical connection therewith.
It is noted that the lead frame 10 of the conventional semiconductor chip package only carries a single integrated circuit chip 11. In view of the rapid advance in semiconductor integrated circuit technology, a fewer number of chips in a system, and even the extreme goal of a single system-on-a-chip (SOC) is desired.
Higher integration of integrated circuits to include as many circuitry as possible into a single semiconductor chip is an effective way of reducing the number of components in a system to shrink the physical size, reducing the power consumption, and increasing the production yield of the system. However, current technology has yet to provide a cost-effective way of achieving this goal of higher integration. For example, a logic integrated circuit that incorporates an embedded DRAM on a single chip always costs much higher than a sole DRAM chip and a sole logic chip. Thus, other alternatives are worthwhile to explore.
One alternative that is currently available is to integrate the circuits in the packaging stage rather than in the semiconductor fabrication stage. A multi-chip module (MCM) packaging approach has been proposed for a high-density package of multiple integrated circuit chips in a single packaged module. For example, U.S. Pat. No. 5,239,448 issued to Perkins et al. teaches the formation of a subsystem by constructing a locally complex area, i.e. a multi-layer MCM carrier, on a flexible carrier, along with other components. U.S. Pat. No. 5,784,264 issued to Tanioka teaches an MCM carrier having wiring layers on front and back surfaces and internally thereof.
It is noted that the MCM packaging approach requires a complicated substrate construction to permit effective integration of the chips thereon, and further requires a lot of additional facilities on the substrate to permit final testing of the packaged module. For example, U.S. Pat. No. 5,784,264 teaches the need to provide a test mode enable bond pad, such as an output enable pad, on each integrated circuit die of an MCM integrated circuit module, a fuse incorporated into the substrate to connect the test mode enable bond pad to a no-connection pin, and a resistor incorporated into the substrate to connect the test mode enable bond pad to a reference voltage pin.
In addition, the MCM packaging approach entails a relatively high cost such that it is worthwhile to be adopted only in a few specific applications.
Therefore, the main object of the present invention is to provide a lead frame for a semiconductor chip package to overcome the aforementioned disadvantages associated with the use of a substrate in the conventional MCM packaging approach.
Another object of the present invention is to provide a semiconductor chip package that is relatively low cost, that has a relatively simple construction, and that integrates multiple integrated circuit chips, especially when the chips are heavily correlated during system operation, such as a logic chip and its associated memory chips, thereby resulting in the advantages of lower feature size, lower power, and higher production yield when using the package in a system board.
A further object of the present invention is to provide a method of fabricating a semiconductor chip package with multiple integrated circuit chips that offers the advantages of lower feature size, lower power, and higher production yield when used in a system board but without the disadvantages of the conventional MCM packaging approach.
According to one aspect of the invention, a lead frame is adapted for use in a semiconductor chip package, and comprises a frame body formed with at least two chip-receiving windows. Each of the chip-receiving windows is adapted to receive a respective integrated circuit chip therein. Internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are adapted to be connected electrically to bonding pads on the integrated circuit chips in the chip-receiving windows such that internal electrical connection among the integrated circuit chips can be established via the internal connection leads. External connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows, and are adapted to be connected electrically to the bonding pads on the integrated circuit chip in said at least one of the chip-receiving windows. The external connection leads serve as terminal pins such that external electrical connection with the integrated circuit chip in said at least one of the chip-receiving windows can be established via the external connection leads.
According to another aspect of the invention, a semiconductor chip package comprises a lead frame including a frame body and at least two chip-receiving windows formed in the frame body. Each of at least two integrated circuit chips is received in a respective one of the chip-receiving windows, and has a plurality of bonding pads thereon. Internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are connected electrically to the bonding pads on the integrated circuit chips in the chip-receiving windows to establish internal electrical connection among the integrated circuit chips. External connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows. The external connection leads are connected electrically to the bonding pads on the integrated circuit chip in said at least one of the chip-receiving windows, and serve as terminal pins such that external electrical connection with the integrated circuit chip in said at least one of the chip-receiving windows is established via the external connection leads.
According to a further aspect of the invention, a method of fabricating a semiconductor chip package comprises: forming a frame body of a lead frame with at least two chip-receiving windows, a plurality of internal connection leads adjacent to the chip-receiving windows, and a plurality of external connection leads adjacent to at least one of the chip-receiving windows; providing at least two integrated circuit chips, and placing each of the integrated circuit chips in a respective one of the chip-receiving windows; connecting electrically the internal connection leads to bonding pads on the integrated circuit chips in the chip-receiving windows to establish internal electrical connection among the integrated circuit chips; and connecting electrically the external connection leads to the bonding pads on the integrated circuit chip in said at least one of the chip-receiving windows, the external connection leads serving as terminal pins such that external electrical connection with the integrated circuit chip in said at least one of the chip-receiving windows is established via the external connection leads.